1. Field of the Invention
The present invention relates to an instruction set of a microcomputer and an executing method of the same by the microcomputer.
2. Description of the Related Art
As an example of prior arts, an instruction set capable of processing two operand sizes of 8-bit length and 16-bit length, and an executing method of the same by a microcomputer is described in the following.
For example, a moving state of data in case of storing a result of content of a register and a content of a memory, which are added by an instruction stored in the microcomputer, into the original register is shown in schematic diagrams of FIG. 1 and FIG. 2. Though each memory address is allocated in a unit of 8 bits in a usual microcomputer, when operands of 16-bit length can be processed, each register has a 16-bit width.
In the case where the operand size is 8-bit, as shown in FIG. 1, an augend consisting of the content of lower 8 bits of a register RG1 of 16-bit length as a first source operand, and an addend consisting of 8-bit data stored in a designated memory address of a memory M as a second source operand are added, and the 8-bit addition result as a destination operand is stored into the lower 8 bits of the register RG1, that is, an original storage of the augend.
Meanwhile, in the case where operand size is 16-bit, as shown in FIG. 2, an augend consisting of the whole content of a register RG2 of 16-bit length, and an addend consisting of a whole of 16-bit data stored in a designated memory address of the memory M and another consecutive memory address are added, and the 16-bit addition result is stored into the entire register RG2, that is, the original storage of the augend.
As such, in case of processing the different operand sizes, for example, in case of processing the 8-bit length or 16-bit length operand size, even the operation is same, instructions corresponding to each occasion are required. In case of executing such instructions by the microcomputer, the following two methods are considered.
A first method is that, different instruction codes, in other words, the instruction codes are allocated uniquely to the instruction operating only the 8-bit length operand and the instruction operating only the 16-bit operand as considering the two as entirely different instructions.
Specifically, as shown in a schematic diagram of an instruction set of FIG. 3, for example, in case of add instruction, for the 8-bit operand, an exclusive add instruction shown by mnemonic "ADD.B", to which "00000000" is allocated, is prepared as the instruction code, and for the 16-bit operand, an exclusive add instruction shown by mnemonic "ADD.W", to which "00000001" is allocated, is prepared as the instruction code.
An end symbol "B" of the mnemonic shows that the operand is a byte size of a 8-bit length, and an end symbol "W" shows that the operand is a word size of a 16-bit length.
In case of subtract instruction, for the 8-bit operand, an exclusive subtract instruction shown by mnemonic "SUB.B", to which "00000010" is allocated, is prepared as the instruction code, and for the 16-bit operand, an exclusive subtract instruction shown by mnemonic "SUB.W", to which "00000011" is allocated, is prepared as the instruction code.
In the first method, for the instructions whose operand sizes are different but basically the operation contents are entirely same, it is necessary to allocate two kinds of instruction codes. Thus, when the instruction code length is, for example, 8-bit length, the instruction code which can be used by 256 at the maximum is divided into half for 8-bit length and 16-bit length, and practically, 128 kinds of instructions can be used. However, when the instruction code is made to be 16-bit length, a more number of instruction codes can be used as compared with the case of 8-bit length. However, in case of lengthening the instruction code length as such, a program size or a data quantity of the program becomes larger, as a result, a memory of the microcomputer for storage requires a large capacity and a processing speed becomes slower, causing a new problem.
A second method is that, only one instruction code is allocated to one operation content, and whether the operand size is 8 bits or 16 bits is instructed by a 1-bit flag register. In this case, when the content of the flag register is "1", the 8-bit length is designated as the operand size for the case executing either of the instructions, and when the content of the flag register is to, the 16-bit length is designated as the operand size for the case executing either of the instructions.
Specifically, as shown in a schematic diagram of FIG. 4, for example, in case of add instruction, only the add instruction shown by mnemonic "ADD", to which "00000000" is allocated, is prepared as the instruction code, and the case of processing the 8-bit operand, the content of flag register is set to "1", and in case of processing the 16-bit operand, the content of flag register is set to "0". In case of subtract instruction, only the subtract instruction shown by mnemonic "SUB", to which "00000001", is allocated is prepared as the instruction code, in case of processing the 8-bit operand, the content of the flag register is set to "1", and in case of processing the 16-bit operand, the content of the flag register is set to "0".
In such second method, though the instruction of 256 kinds can be used practically even the instruction code length is 8 bits, the instruction for setting/resetting the flag register to "1" or "0" is required separately. Also, at the time of programming, it is problematic in that, a programmer has to always keep in mind to which value of the flag register is set to make the correct programs.
Next, as another example of the prior arts, a moving state of data in case of executing operation, for example, addition to a content of the register and a content of a memory, and storing the result into the original register or the original memory is shown in FIG. 5 and FIG. 6.
In case of storing the operation result into the register, as shown in FIG. 5, an augend consisting of the content of an 8-bit length register RG3 as a first source operand, and an added constituting of 8-bit data stored in designated memory address of a memory M as a second source operand are added, and the 8-bit addition result as a destination operand is stored into the register RG3, that is, the original storage (the first source operand) of the augend.
Meanwhile, in case of storing the operation result into the memory, as shown in FIG. 6, an augend consisting of the content of the register RG3 as the first source operand, and an addend consisting of 8-bit data stored in the designated memory address of the memory M as the second source operand are added, and the 8-bit addition result as the destination operand is stored into the memory M, that is, the original storage (the second source operand) of the addend.
As such, in case of processing the different storing destinations of the operation result, that is, the destination by even the same operation, for example, when processing either the case where the destination as aforementioned is the register as the first source operand, or the case where it is the memory as the second source operand, the instructions corresponding to each case are required. And, in case of executing a plurality of such instructions by the microcomputer, the following two methods can be considered.
One method is that, as considering an instruction whose destination operand is the first source operand, and an instruction whose destination operand is the second source operand as the entirely different instructions, the instruction code is allocated to each uniquely.
Specifically, as shown in a schematic diagram of FIG. 7, for example, in the add instruction, an exclusive add instruction shown by mnemonic "ADD.1", to which "00000000" is allocated, is prepared as the instruction code for the instruction whose destination is the first source (register), and for the instruction whose destination is the second source (register), an exclusive add instruction shown by mnemonic "ADD.2", to which "00000001" is allocated, is prepared as the instruction code.
And end numeral "1" of the mnemonic shows that the destination is the first source or the register, and an end numeral "2" of the mnemonic shows that the destination is the second source or the memory.
In the subtract instruction, an exclusive subtract instruction shown by mnemonic "SUB.1", to which "00000010" is allocated, is prepared as the instruction code for the instruction whose destination is the first source, and for the instruction whose destination is the second source, an exclusive subtract instruction shown by mnemonic "SUB.2", to which "00000011" is allocated, is prepared as the instruction code.
In the first method, for the instruction whose destinations are different but basically the operation contents are entirely same, it is necessary to allocate two kinds of instruction codes, thus the same problem as the aforementioned first method in case of different operand sizes is encountered.
The second method is that, only one instruction code is allocated to one operation contents, and whether the destination is the first source or the second source is instructed by a 1-bit flag register. In this case, for example, when the content of the flag register is "1", the first source is designated as the destination for the case executing either of the instructions having two operand sources, and when the content of the flag register is "0", the second source is designated as the destination for the case executing either of the instructions.
Specifically, as shown in a schematic diagram of FIG. 8, for example, in the add instruction, only the add instruction shown by the mnemonic "ADD", to which "00000000" is allocated, is prepared as the instruction code, and in case of processing the instruction whose destination is the first source, the content of the flag register is set to "0", and in case of processing the instruction whose destination is the second source, the content of the flag register is set to "0". Also, in the subtract instruction, only the subtract instruction shown by the mnemonic "SUB", to which "00000001" is allocated, is prepared as the instruction code, and when processing the instruction whose destination is the first source, the content of the flag register is set to "1", and when processing the instruction whose destination is the second source, the content of the flag register is set to "0".
In such second method, though practically the instructions of 256 kinds can be used even when the instruction code length is 8 bits, the same problem as the case of aforementioned second method where the operand sizes are different is encountered.
As such, in the conventional instruction set of the microcomputer, in case of plural operand sizes when executing the practically same operations, or in case of plural operand sizes when executing of the operation result, the instructions corresponding to either cases were prepared or either of the instructions is selected by a set value of the flag register. And hence, in the former, the number of instructions which can be used practically reduces to one half of less as compared with the number of instructions which can be set, and in the latter, a burden of an programmer is heavy at programming.
The present invention has been devised in diagram of such circumstances, therefore, it is an object thereof to provide an instruction set and an executing method of the same by a microcomputer, whereby the number of instructions which can be used is made practically same as the number of instructions which can be set, both for the case where operand sizes of the instructions to be operated are plural, and the case where the number of storages of the operation result is plural, thus the burden of the programmer at programming can be lessened.